Cadence

2655 Seely Rd.
San Jose, CA 95134
USA
Website: www.cadence.com

 

Platform and Cadence

The integration of Platforms LSF’s Distributed Resource Management (DRM) capabilities with Cadence's computational intensive programs provide customers with the ability to perform simulation and verification in a shorter period of time.

 

Using Platform LSF, jobs can be run across a wide variety of desktop and server class machines without the fear of losing valuable time due to interruption of jobs by higher-priority work, machine failure, or network outages.

 

Platform LSF also maximizes the distribution and throughput of Cadence's applications, both sequential and distributed, allowing customers to make better use of existing hardware to save valuable time in simulation and verification. Ultimately, customers have the ability to add more features, perform more testing or release the product to market earlier.

 

Platform Products

·        Platform LSF

 

Cadence Products

·         Build Gates: A synthesis tool that delivers dramatic performance and productivity benefits over conventional synthesis tools, yielding superior quality of results with less manual intervention. This is why leading IC design companies and silicon vendors have rapidly adopted it as their synthesis tool of choice for fully exploiting silicon process technology advances.

 

·         Virtuoso® Analog Design Environment: The analog design and simulation environment for the Virtuoso custom design platform. It is the industry's standard task-based environment for simulating and analyzing full-custom, analog, and RF IC designs. Virtuoso Analog Design Environment features a graphic user interface, integrated waveform display and analysis, distributed processing, and interfaces to popular third-party simulators.

 

·         Assura™ Design Rule Checker (DRC): Part of the design verification suite of tools within the Virtuoso® custom design platform. Assura DRC is a full-featured tool that supports both interactive and batch operation modes and utilizes hierarchical processing for fast, efficient identification and correction of design rule errors in even the most advanced designs.

 

·         Assura™ Layout vs. Schematic (LVS) Verifier: Part of the design verification suite of tools within the Virtuoso® custom design platform, Assura LVS ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout by automatically extracting devices and nets formed across layout hierarchy and comparing them to the schematic netlist. Assura LVS provides fast, efficient verification in both interactive and batch mode.

 

·         NC-Verilog: The industry's premier Verilog simulator, delivering high performance and capacity with transaction/signal viewing and integrated coverage analysis. NC-Verilog is fully compatible with the Incisive™ unified simulator, providing an easy upgrade path to comprehensive digital verification for nanometer-scale ICs.

 

·         NC-VHDL: The industry's premier VHDL simulator, delivering high performance and capacity with transaction/signal viewing and integrated coverage analysis. NC-VHDL is fully compatible with the Incisive unified simulator, providing an easy upgrade path to comprehensive digital verification for nanometer-scale ICs.

 

·         MercuryPlus: Based on a custom field-programmable gate array (FPGA) optimized for emulation, this solution achieves industry-leading compile time performance, capacity, debug productivity, and circuit modeling accuracy, often delivering three or more design turns per day.

 

·         Verifault-XL: A flexible and reliable tool that enables you to develop tests that can detect all of the possible faults in your circuit designs.

 

·         Virtuoso Neocircuit: Performs automatic circuit sizing and optimization for custom digital, RF and mixed-signal circuits. Integrated with the Cadence® Virtuoso custom design platform, Virtuoso NeoCircuit employs the designer's simulator of choice to size, bias, and verify circuits interactively with a manual starting point or automatically without a starting point.

 

·         Vmanager: A VPA system for process and verification closure management

 

·         Specman Elite: Capture the rules from specifications and use this info to automate the functional verification process. Specman Elite's methodology finds the "bugs you haven't thought of" in your Verilog or VHDL design caused primarily by ambiguities in the spec, or unanticipated usage by the target system. The result? Faster verification and higher quality products.

 

About Cadence

Cadence is the world's largest supplier of electronic-design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics-based products. With approximately 4,900 employees and 2004 revenues of approximately $1.2 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN.

 

 

 


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